------------------------------------------------------------------------------------------------------------------------------------------- Multiple CPU Assembly Mnemonic Table v0.1 210299/GPZ-HIT ------------------------------------------------------------------------------------------------------------------------------------------- Registers: ---------- A : akku F : flag-register B,C,D,E,H,L : 8080/z80 registers X,Y : 6502/6510 index registers SP : 8080/z80 Stack Pointer AF,BC,DE,HL : 8080/z80 register pairs PSW : alias for the AF register pair on 8080 M : alias for the HL register pair on 8080 Flags: ------ Z : zero flag C : carry flag H : 8080/z80 half-carry flag (carry from least significant nibble) N : 6502 negative (sign) flag 8080/z80 substract flag (?!) Arguments: ---------- x8 : 8 bit constant that is implied with the opcode p8 : 8 bit Port-Address r8,r8' : one of the 8 bit registers r16,r16' : one of the register-pairs/16 bit registers m8,m8' : 8 bit memory adress or offset (eg zeropage adressing modes) i8,i8' : 8 bit immediate value m16,m16' : 16 bit memory adress i16,i16' : 16 bit immediate value markers: -------- ~ : opcode doesnt exactly match the comparison * : opcode is undocumented ('illegal') ------------------------------------------------------------------------------------------------------------------------------------------- Gameboy note: ------------- zero-page location: $ff00-$ffff (only $ff80-$ffff useable) stack-location: set by user, SP after reset: $ffff opcode-syntax referring to: Rednex Gameboy Development System (asMotor of RGBDS) 6502 note: ---------- since there is no HL register for pointers, absolute memory adresses are used instead. Also 6502 cpu's dont have the (limited) support for 16-bit stuff like some other 8 bit cpu's (aka register-pairs) so respective opcodes work in 8 bit only. zero-page location: $0000-$00ff (only $0002-$00ff useable) stack-location: $0100-$01ff (fixed), SP after reset: $01ff opcode-syntax referring to: Omikron Turbo Assembler (c64) ------------------------------------------------------------------------------------------------------------------------------------------- 8080 Z80 Gameboy(~z80) 6502/6510 ------ ------ --------------- ----------- loading/storing data: --------------------- MVI r8 [i8] LD r8, i8 LD r8, i8 LDA #i8 / LDX #i8 / LDY #i8 MOV r8, r8' LD r8, r8' LD r8, r8' TAX / TXA / TAY / TYA / TXS / TSX LDA [m8] [m8'] LD A, (m16) LD A, [m16] LDA m16 LDAX B LD A, (BC) LD A, [BC] - LDAX D LD A, (DE) LD A, [DE] - LHLD [m8] [m8'] LD HL, (m16) LD HL, [m16] - LXI B [i8] [i8'] LD BC, i16 LD BC, i16 - LDID [i8] [i8'] LD DE, i16 LD DE, i16 - LXI H [i8] [i8'] LD HL, i16 LD HL, i16 - STA [m8] [m8'] LD (m16), A LD [m16], A STA m16 SHLD [m8] [m8'] LD (m16), HL LD [m16], HL - STAX B LD (BC), A LD [BC], A - STAX D LD (DE), A LD [DE], A - MOV M, r8 LD (HL), r8 LD [HL], r8 - MOV r8, M LD r8, (HL) LD r8, [HL] - MVI M [i8] LD (HL), i8 LD [HL], i8 - store via HL and inc. HL - - LDI [HL],A - load via HL and inc. HL - - LDI A,[HL] - store via HL and dec. HL - - LDD [HL],A - load via HL and dec. HL - - LDD A,[HL] - load from zeropage - - LDH A,[$ff00+m8] LDA $00+m8 store to zeropage - - LDH [$ff00+m8],A STA $00+m8 load indexed from zeropage - - LD A,[$ff00+C] LDA $00,Y store indexed to zeropage - - LD [$ff00+C],A STA $00,Y logical instructions: --------------------- logical AND ANA M AND (HL) AND [HL] ~AND m16 " ANA r8 AND r8 AND r8 - " ANI [i8] AND i8 AND i8 AND #i8 logical OR ORA M OR (HL) OR [HL] ~OR m16 " ORA r8 OR r8 OR r8 - " ORI [i8] OR i8 OR i8 ORA #i8 logical EXCLUSIVE OR XRA M XOR (HL) XOR [HL] ~EOR m16 " XRA r8 XOR r8 XOR r8 - " XRI [i8] XOR i8 XOR i8 EOR #i8 arithmetic instructions: ------------------------ dec. byte in memory - - DEC [HL] ~DEC m16 dec. register DCR r8 DEC r8 DEC r8 DEX / DEY dec. register-pair DCX B DEC BC DEC BC - " DCX D DEC DE DEC DE - " DCX H DEC HL DEC HL - inc. byte in memory INR M INC (HL) INC [HL] ~INC m16 inc. register INR r8 INC r8 INC r8 INX / INY inc. register-pair INX B INC BC INC BC - " INX D INC DE INC DE - " INX H INC HL INC HL - add with carry ACI [i8] ADC A, i8 ADC A, i8 ADC #i8 " ADC M ADC A, (HL) ADC A, [HL] ~ADC m16 " ADC r8 ADC A, r8 ADC A, r8 - add ADD M ADD A, (HL) ADD A, [HL] ~CLC ; ADC m16 " ADD r8 ADD A, r8 ADD A, r8 - " ADI [i8] ADD A, i8 ADD A, i8 CLC ; ADC #i8 " DAD B ADD HL, BC ADD HL, BC - " DAD D ADD HL, DE ADD HL, DE - " DAD H ADD HL, HL ADD HL, HL - substract with carry SBB M SBC A, (HL) SBC A, [HL] SBC m16 " SBB r8 SBC A, r8 SBC A, r8 - " SBI [i8] SBC A, i8 SBC A, i8 SBC #i8 substract SUB M SUB (HL) SUB [HL] ~SEC ; SBC m16 " SUB r8 SUB r8 SUB r8 - " SUI [i8] SUB i8 SUB i8 SEC ; SBC #i8 compares: --------- comp. with memory CMP M CP (HL) CP [HL] ~CMP m16 comp. with register CMP r8 CP r8 CP r8 - comp. with immediate byte CPI [i8] CP i8 CP i8 CMP #i8 bit-shifts: ----------- shift left with Carry RAL RLA RLA ROL A " - - RL r8 - shift right with Carry RAR RRA RRA ROR A " - - RR r8 - shift left - - SLA ASL A shift right - - SRL LSR A RLC RLCA RLCA - - - RLC r8 - RRC RRCA RRCA - - - RRC r8 - - - SRA - misc operations on registers: ----------------------------- Complement A CMA CPL CPL EOR #$ff Decimal Adjust A DAA DAA DAA - Swap low and high nibble - - SWAP r8 - exchange DE and HL XCHG EX DE, HL - - setting/resetting flags: ------------------------ Set Carry Flag STC SCF SCF SEC Clear Carry Flag STC ; CMC SCF ; CCF SCF ; CCF CLC Complement Carry Flag CMC CCF CCF - far branch: ----------- jump to address JMP [m8] [m8'] JP m16 JP m16 JMP m16 jump indirekt via pointer PCHL JP (HL) JP [HL] ~JMP (m16) far conditional branch: ----------------------- branch if Z==1 JZ [m8] [m8'] JP Z, m16 JP Z, m16 BNE *+3 ; JMP m16 Z==0 JNZ [m8] [m8'] JP NZ, m16 JP NZ, m16 BEQ *+3 ; JMP m16 C==1 JC [m8] [m8'] JP C, m16 JP C, m16 BCC *+3 ; JMP m16 C==0 JNC [m8] [m8'] JP NC, m16 JP NC, m16 BCS *+3 ; JMP m16 JM [m8] [m8'] JP M, m16 - - JP [m8] [m8'] JP P, m16 - - JPE [m8] [m8'] JP PE, m16 - - JPO [m8] [m8'] JP PO, m16 - - near conditional branch: ------------------------ branch if Z==1 - - JR Z, m16 BEQ m16 Z==0 - - JR NZ, m16 BNE m16 C==1 - - JR C, m16 BCS m16 C==0 - - JR NC, m16 BCC m16 - - - - - - - - - - - - - - - - subroutine call: ---------------- CALL [m8] [m8'] CALL m16 CALL m16 JSR m16 conditional subroutine call: ---------------------------- call if Z==1 CZ [m8] [m8'] CALL Z, m16 CALL Z, m16 BNE *+3 ; JSR m16 Z==0 CNZ [m8] [m8'] CALL NZ, m16 CALL NZ, m16 BEQ *+3 ; JSR m16 C==1 CC [m8] [m8'] CALL C, m16 CALL C, m16 BCC *+3 ; JSR m16 C==0 CNC [m8] [m8'] CALL NC, m16 CALL NC, m16 BCS *+3 ; JSR m16 CM [m8] [m8'] CALL M, m16 - - CP [m8] [m8'] CALL P, m16 - - CPE [m8] [m8'] CALL PE, m16 - - CPO [m8] [m8'] CALL PO ,m16 - - subroutine return: ------------------ RET RET RET RTS conditional subroutine return: ------------------------------ return if Z==1 RZ RET Z RET Z BNE *+1 ; RTS Z==0 RNZ RET NZ RET NZ BEQ *+1 ; RTS C==1 RC RET C RET C BCC *+1 ; RTS C==0 RNC RET NC RET NC BCS *+1 ; RTS RM RET M - - RP RET P - - RPE RET PE - - RPO RET PO - - interupt related instructions: ------------------------------ set irq flag (irq's off) DI DI DI SEI clear irq flag (irq's on) EI EI EI CLI issue a hard irq RST RST x8 RST x8 BRK i/o specific: ------------- Get Byte from In-Port IN [p8] IN A, (p8) - - Send Byte to Out-Port OUT [p8] OUT (p8), A - - stack related: -------------- put reg. on Stack PUSH B PUSH BC PUSH BC - PUSH D PUSH DE PUSH DE - PUSH H PUSH HL PUSH HL - PUSH PSW PUSH AF PUSH AF PHA ; PHP get reg. from Stack POP B POP BC POP BC - POP D POP DE POP DE - POP H POP HL POP HL - POP PSW POP AF POP AF PLP ; PLA load Stack Pointer LXI SP [i8] [i8'] LD SP, i16 LD SP, i16 LDX #i8 ; TXS SPHL LD SP, HL LD SP, HL - - - LD [m16], SP - - - LD HL,SP+n - dec. Stack-Pointer DCX SP DEC SP DEC SP TSX ; DEX ; TXS inc. Stack-Pointer INX SP INC SP INC SP TSX ; INX ; TXS DAD SP ADD HL, SP ADD HL, SP - add to Stack-Pointer - - ADD SP, i8 TSX ; TXA ; CLC ; ADC #i8 ; TAX ; TXS XTHL EX (SP), HL - - misc: ----- No Operation (Delay) NOP NOP NOP NOP halt operation (until irq) HALT HLT HLT *JAM stop cpu (until exception) - - STOP *JAM -------------------------------------------------------------------------------------------------------------------------------------------